In the field of resistive-switching Random Access Memory (RRAM) devices, a Conductive Bridging Random Access Memory (CBRAM) device is considered a valuable non-volatile storage technology. It offers high endurance, reduced variability and good scalability.
A CBRAM device contains an insulating layer sandwiched between an active top electrode providing metal cations, e.g. Cu+ or Ag+, and an inert bottom electrode that does not provide such metal cations. The operation of the CBRAM device relies on the voltage-induced redox-based formation and rupture of a metal-based, e.g. Cu or Ag, conductive filament (CF) in the insulating layer acting as a solid state electrolyte.
When an electrical field is applied between both top and bottom electrodes, metal cations provided by the active top electrode drift towards the opposite inert bottom electrode through the insulating layer thereby forming the conductive filament. As a result, during operation, the CBRAM device can be reversibly switched between a high resistive (HRS) or reset state and a low resistive (LRS) or set state.
After manufacturing the CBRAM device and before putting it into operation, a forming step is applied to each CBRAM device to create an initial conductive filament therein. Such a forming step requires a current pulse having a long pulse width and a large pulse height, typically more than 50 uA during 1 second or more. These forming conditions make the forming step a time-consuming process.
In addition, the current conditions of this forming step determine the programming current conditions, as typically the same high current level is used for forming and for programming to improve the memory window of the CBRAM device, i.e. the difference in resistance between the reset and set state.
These current conditions also determine the feasibility of using CBRAM as a replacement for flash memory devices, requiring both fast programming times, low forming/programming current densities and a sufficient memory window.
Hence, there is a need for a CBRAM device that does not suffer from one or more of the above shortcomings of the state-of-the-art CBRAM devices.
Preferably such CBRAM device should be manufactured in a CMOS compatible way.